EMBEDDED CO-DESIGN CONTROL PLANE

Hardware-to-firmware with evidence, not assumptions.

Analyze schematic netlists, generate firmware, build, and verify in a governed workflow.

Offline Technical Preview
omera-cli — bash
$ omera chat
Omera 3.6 — Chat REPL (Autonomous Mode)
Session: a7f3c… | Context: 12,480 tokens

You > What peripherals does my STM32F407 expose on connector J3?

Omera 3.6 > Based on the system map, connector J3 exposes:
  • SPI1 (PA5/SCK, PA6/MISO, PA7/MOSI)
  • I2C1 (PB6/SCL, PB7/SDA)
  • USART2 (PA2/TX, PA3/RX)

You >
View VS Code Extension Interface
my-project — Visual Studio Code
main.cplatformio.ini
// Auto-generated by Omera 3.6#include "stm32f4xx_hal.h"void SystemClock_Config(void);static void MX_GPIO_Init(void);static void MX_USART2_UART_Init(void);int main(void) { HAL_Init(); SystemClock_Config(); MX_GPIO_Init(); MX_USART2_UART_Init();...}
You: Expose SPI1 on PA5-PA7.
Omera 3.6: Added pin definitions:
PA5 -> SPI1_SCK
PA6 -> SPI1_MISO
PA7 -> SPI1_MOSI
SUPPORTED MCUS & TOOLCHAINS
STM32Validated
Analyze & GenValidated
Compile / BuildValidated
SimulationValidated
ESP32Preview / Validated
Analyze & GenValidated
Compile / BuildValidated
SimulationPreview
RP2040Preview / Validated
Analyze & GenValidated
Compile / BuildValidated
SimulationPreview
ArduinoPartial Support
Analyze & GenValidated
Compile / BuildValidated
SimulationNot Available
PIPELINE FLOW

How Omera Firmware Works

A unified automation pipeline integrating physical circuits to embedded code.

01

Understand Hardware

Import EDA netlists (KiCad/Altium), auto-detect target MCUs, and classify board pin configurations.

02

Assess Safety

Analyze critical signal networks and evaluate peripheral pin constraints before generation.

03

Resolve Architecture

Map compatible driver packages to hardware components and output structural plans.

04

Build & Simulate

Compile code via PlatformIO and run deterministic host-side firmware simulation traces.

05

Verify & Package

Execute static and dynamic validation gates and package artifacts into a ZIP Evidence Pack.

OMERACODE / SYSTEM MAP DETECTOR

Visualizing the Hardware-Firmware Boundary

Every view is generated from versioned project artifacts—not drawn as a decorative architecture diagram.

View Hardware Map
Source: board_profile.json

MCU Pin Mappings

PA9USART1_TXFT232R USB Bridge
PA10USART1_RXFT232R USB Bridge
PA5SPI1_SCKSSD1306 OLED Display
PA7SPI1_MOSISSD1306 OLED Display

Electrical Connectivity Graph

[STM32F407]
  ├── (SPI1) ──> [SSD1306 OLED]
  ├── (USART1) <═> [FT232R USB Bridge]
  └── (I2C1) ──> [BME280 Sensor]
            
View Firmware Interaction
Source: firmware_plan.json

FreeRTOS Task Scheduler

Manages core application runtime tasks and execution cycles.

Task 1TelemetryLoggerTask (Period: 100ms, Priority: 3)
Task 2DisplayUpdaterTask (Period: 500ms, Priority: 1)

Peripheral Drivers

+------------------+     +------------------+
|   stm32f4xx_hal  | --> |   BME280 Driver  |
+------------------+     +------------------+
|   SSD1306 Driver | --> |   FDCAN Driver   |
+------------------+     +------------------+
            
View Simulation Trace
Source: sim_report.json
[+0.000s] [INFO] CPU clock configured: 168MHz
[+0.002s] [INFO] Peripheral I2C1 initialized at 400kHz
[+0.015s] [INFO] Display SSD1306 successfully initialized via SPI1
[+0.050s] [INFO] FreeRTOS task scheduler started
[+0.100s] [PASS] TelemetryLoggerTask read sensor BME280: T=24.5C, H=50.2%
[+0.500s] [PASS] DisplayUpdaterTask flushed frame buffer to screen
[+1.000s] [PASS] Runtime simulation completed with 0 errors
View Verification Diff
Source: verification_state.json
PASSSPI1 Pin Mapping Match: PA5/PA6/PA7 bindings verified on KiCad netlist.
PASSFreeRTOS Heap Allocation: Allocation meets safety margins (25% remaining).
PASSHAL Clock Validation: 168MHz core clock matches simulation constraints.
PASSSafety Perimeter Checked: Actuator safety line verified with zero conflicts.
ITERATIVE RECOVERY

Build, Debug and Recover Loop

Intelligent, automated build diagnostics and patching under human control.

No more tedious manual debugging. When compilation fails, Omera 3.6 analyzes the build log and proposes automated patch drafts.

  • Build Explain: AI parses compiler errors and explains root causes in plain language.
  • Proposed Changes: Generates isolated code or configuration changes (draft patches).
  • Human Review Required: Draft patches are applied only after manual review and human approval.
  • Re-Verify: Re-builds automatically to verify compilation passes the safety gate.
Build Diagnostics
$ omera fw build run
[ERROR] main.c:12: undefined reference to 'HAL_FDCAN_Init'
$ omera fw build explain
> Compilation failed due to missing FDCAN library in platformio.ini.
$ omera fw patch draft
> Draft patch generated. Review differences before applying:
  + lib_deps = stm32_fdcan_hal
COMPLIANCE & GOVERNANCE

Evidence and Governance

Rigorous safety controls and structural boundary validation.

Command Risk & Confirmation Policy

Command GroupExample CommandConfirmation
Read-only`doctor`, summary, inspectOptional
Generate artifact / buildbuild, generate, draft patchPolicy-based
Modify source codeapply patchRequired
Hardware interactiondebug, flashRequired
Destructive / Adminrevoke, delete, overwriteRequired

Workspace Sandbox

The AI agent is restricted to files within the active workspace. Choke points block Path Traversal and Symlink Escape.

Evidence Pack Export

Exports secure ZIP Evidence Packs containing logs, checksums, and test runs (not a compliance certification).

INTEGRATED INTERFACES

One Workflow, Two Ways of Working

Select the interface that fits your engineering workflow.

>_

Omera CLI

Designed for automation, CI/CD pipelines, bulk scripting, hardware flashing, and admin tasks.

  • ✓ 55 commands
  • ✓ REPL chat & slash commands
  • ✓ TUI Dashboard
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VS Code Extension

Visual project workspace, interactive system maps, side-by-side diffing, and log visualizer.

  • ✓ 3 Panels (Control, Copilot, RUN)
  • ✓ Interactive System Map
  • ✓ Visual Diff View
REAL-WORLD APPLICATIONS

Use Cases

How embedded engineers accelerate delivery with Omera Firmware.

IoT Sensor Node Firmware (ESP32-S3)

Initialize ESP32-S3 firmware, read BME280 sensor data over I2C, transmit telemetry via UART, and configure deep sleep cycles.

Build Failure Recovery (STM32)

Diagnose missing HAL driver links from build logs, generate platformio.ini patch drafts, and recover the build.

Board Log Analysis

Import CSV/LOG data from hardware test runs, evaluate cycle times, and suggest optimal register values.

Evidence Packaging for Audit

Collect static analysis logs, Renode simulation reports, and verification states into a signed ZIP artifact.

DATA SECURITY

Security & Deployment Modes

Govern your project data. All AI actions are routed under Omera 3.6.

Local Mode

Run Omera 3.6 on infrastructure you control. Data does not leave your local network when configured with a local inference engine.

BYOK Mode

Provide your own API keys. AI processing data goes directly to the configured AI provider, bypassing the Omera Account Backend.

Omera Account Mode

Backend routes requests, manages usage limits, and entitlement. Users always interact with Omera 3.6.

Credential Protection

Credentials are encrypted in VS Code SecretStorage or protected via OS file permission 0600.

PRICING

Pricing Plans

Start free, scale as your project demands.

Explore

Free

$0/mo
50 AI messages | 32K context
  • ✓ 50 AI messages / month
  • ✓ 0 Nexus Runs
  • ✓ 32K token context window
  • ✓ Full System Map visibility
  • ✓ Free CLI & Extension access
Individual

Pro

$20/mo
5,000 AI messages | 200K context
  • ✓ 5,000 AI messages / month
  • ✓ 500 Nexus Runs / month
  • ✓ 200K token context window
  • ✓ Nexus AI Engine access
  • ✓ Swarm Repair capability
  • ✓ Priority support
Development Team

Team

$500/mo
50,000 AI messages | 1M context
  • ✓ 50,000 AI messages / month
  • ✓ 5,000 Nexus Runs / month
  • ✓ 1M token context window
  • ✓ Dedicated support manager
  • ✓ Team workspace sync

Preview limits. Final entitlements are confirmed at checkout. Looking for full feature comparisons? View the complete pricing table here.

FAQ

Frequently Asked Questions

What kinds of tasks can Omera handle?

Omera excels at analyzing EDA netlists, generating peripheral driver code, building firmware via PlatformIO, running host-side simulation traces on Renode, and packaging evidence artifacts. It is purpose-built for the hardware-to-firmware boundary.

How does Omera work with my existing tools?

Omera CLI runs in your terminal alongside any IDE. The VS Code Extension integrates directly into your editor with dedicated panels. Both interfaces work with PlatformIO, KiCad, Altium netlists, and standard Git workflows without requiring changes to your process.

Is my source code secure?

Yes. In Local Mode, data never leaves your machine. In BYOK Mode, requests go directly to your configured AI provider. In all modes, the workspace sandbox enforces strict directory boundaries and only pre-authorized CLI commands are permitted. Credentials are stored using VS Code SecretStorage or OS-level file permissions.

Does Omera replace compliance certification?

No. Omera generates Evidence Packs containing build logs, test reports, and verification results to assist with internal design reviews. OmeraCode is not a certification body and does not replace official CE, FCC, ISO, or IEC compliance testing.

What are the system requirements?

Omera CLI works on macOS, Linux, and Windows. The VS Code Extension requires VS Code 1.80+. PlatformIO Core is required for firmware compilation. An internet connection is needed for Account Mode and BYOK Mode; Local Mode works fully offline.

GET STARTED

Start building in minutes

Choose your preferred interface and begin your first hardware analysis.

Terminal

$ npm install -g @omeraeda/cli
$ omera doctor
$ omera chat

Requires Node.js 18+ and PlatformIO Core.

VS Code

Search "Omera" in the Extensions panel,
or install from the VS Code Marketplace.

Requires VS Code 1.80+ and PlatformIO IDE extension.